In a semiconductor memory device, such as a dynamic random access memory (DRAM) device, fuse elements are provided along with each memory cell array. Sometimes a fuse line of each fuse element also constitutes a bit line. In a products test of a semiconductor memory device, when malfunction of a memory cell is detected in a memory cell array, the fuse line of the fuse element relating to the memory cell having malfunction is melted down using a laser beam. Thereby, it becomes possible to replace the memory cell having malfunction with another normal memory cell, and a memory device which included the memory cell having malfunction can be repaired into a memory device having complete function.
Here, in a products test of a semiconductor memory device, when bit lines including defective memory cells are replaced with other bit lines having normal cells by melting down fuse elements using laser beams, a ratio of the number of addresses normally repaired to the number of addresses including defective memory cells is called as a P/W rate. Of course, the P/W rate should be as higher as possible.
With respect to FIG. 5, an explanation will be made on a structure of a fuse element used in a conventional memory device. FIG. 5 is a cross sectional view showing a structure of a fuse element used in a conventional memory device.
As shown in FIG. 5, a fuse element 30 comprises a fuse line portion 34 formed on a grounding layer 32. On the fuse line portion 34, a laminated structure 36 is formed. The fuse element 30 also comprises a first opening portion 38 which is formed by partially etching and opening the laminated structure 36 on the fuse line portion 34. The fuse element 30 further comprises a cover layer 40 which coats the surface portion of the fuse element 30 including inner walls of the opening portion 38. Also, a second opening portion 42 is formed by etching and opening the cover layer 40 at the bottom portion of the first opening portion 38 and a portion of the laminated structure 36. It should be noted that the fuse element is elongated in the direction perpendicular to the sheet of the drawing.
The laminated structure 36 is formed by sequentially forming a first SiO2 film or layer 44, a first BPSG (Boron-doped Phosphor-Silicate Glass) film or layer 46, a second SiO2 film or layer 48, a third SiO2 film or layer 50, a second BPSG film or layer 52, a fourth SiO2 film or layer 54, and a fifth SiO2 film or layer 56, on the fuse line portion 34.
The first opening portion 38 is formed by penetrating through the fifth SiO2 layer 56 and the fourth SiO2 layer 54 and by partially digging down the upper layer portion of the second BPSG layer 52. The second opening portion 42 is formed by penetrating through the cover layer 40 and by further digging down the second BPSG layer 52 partially, at the bottom portion of the first opening portion 38 over the fuse line portion 34.
Also, on the second BPSG layer 52, there are provided tungsten wirings 58.
With reference to FIG. 5, an explanation will be given on a method of manufacturing the conventional fuse element 30.
First, a fuse line portion 34 is formed on a grounding layer 32 such as an insulating layer formed on a semiconductor wafer. Then, on the fuse line portion 34, a first SiO2 layer 44 and a first BPSG layer 46 are sequentially formed. Thereafter, a first CMP (Chemical Mechanical Polishing) processing is performed on the first BPSG layer 46 to planarize the top surface thereof. Then, on the planarized first BPSG layer 46, a second SiO2 layer 48, a third SiO2 layer 50 and a second BPSG layer 52 are sequentially formed. Thereafter, a second CMP processing is performed on the second BPSG layer 52 to planarize the top surface thereof.
Next, tungsten wirings 58 are formed on the second BPSG film 52, by using well known photolithography process and etching process. With respect to memory (DRAM) cells, not shown in the drawing, fabricated on the semiconductor substrate on which the fuse element 30 is also fabricated, capacitors of the memory cells are formed after the above-mentioned planarization of the first BPSG layer 46.
Further, as interlayer insulating films or layers for forming a metal layer therebetween, a fourth SiO2 layer 54 and a fifth SiO2 layer 56 are sequentially formed on the second BPSG layer 52.
Then, by using photolithography process and etching process, first opening portion 38 is formed by penetrating through the fifth SiO2 layer 56 and the fourth SiO2 layer 54 and by partially digging down an upper layer portion of the second BPSG layer 52. It should be noted that formation of the first opening portion 38 is performed simultaneously with formation of through holes (not shown) on the predetermined portions of the tungsten wirings 58. Also, if necessary, other tungsten wirings (not shown) are formed on the fifth SiO2 layer 56, by using photolithography process and etching process, and are connected to the tungsten wirings 58 via the through holes mentioned above. Thereafter, a cover layer 40 is formed on the fifth SiO2 layer 56 as well as on inner walls of the first opening portion 38, and on the other tungsten wirings if they are formed.
Lastly, by using photolithography process, the second opening portion 42 is formed by etching through the cover layer 40 and by further etching down an upper portion of the second BPSG layer 52, at the bottom portion of the first opening portion 38 over the fuse line portion 34.
The above-mentioned conventional fuse element has the following disadvantages.
That is, when the above-mentioned fuse element is manufactured, CMP processing is performed on each of the first BPSG layer 46 and the second BPSG layer 52. Therefore, dispersion of film thickness of each of the BPSG films occurs every time CMP processing is performed. The thickness of the layers remaining on the fuse line portion 34 is controlled twice by controlling etching rate and etching time when forming the first opening portion 38 and the second opening portion 40.
As a result, the thickness of the layers remaining on the fuse line portion 34 disperses widely every memory chip or every semiconductor wafer. Therefore, it was impossible to obtain high P/W repair rate and to improve manufacturing yield of products.
More particularly, the inventor of this invention carefully studied the disadvantages of the conventional fuse element, and investigated the causes of dispersion of the thickness of the layers remaining on the fuse line portion and of deterioration of the P/W repair rate. As a result, it was found that, since CMP is performed twice to planarize the two BPSG layers, the thickness of each of the BPSG layers disperses every time CMP is performed and thereby dispersion of the thickness of the interlayer films on the fuse line portion becomes large, so that P/W repair rate deteriorates. Further, since the thickness of the layers left on the fuse line portion is controlled twice in the etching processes, that is, the etching process for forming the first opening portion and the etching process for forming the second opening portion, dispersion of the thickness of the layers left on the fuse line portion further becomes large. Due to these causes, uniformity of the thickness of the layers remaining on the fuse line portion is deteriorated.
Therefore, it becomes difficult to uniformly and stably melt down each fuse line portion when trimming is performed for replacing defective memory cells with normal cells, so that P/W repair rate is deteriorated.
In another way, in a manufacturing process of the conventional fuse element mentioned above, it is considered possible to omit the formation process of the first opening portion 38 and to form an opening by one time etching process until an upper portion of the second BPSG layer 52, after forming the cover layer 40. That is, by using photolithography process, the cover layer 40, the fifth SiO2 layer 56, the fourth SiO2 layer 54 and an upper portion of the second BPSG layer 52 are etched in one time. In this case, the thickness of the layers remaining on the fuse line portion is controlled in one time etching process. However, in such method, since the thickness of the layers to be removed by one time etching is too thick, it becomes difficult to precisely control the thickness of the layers remaining on the fuse line portion, instead of becoming easy. Further, the uniformity of the thickness of the layers remaining on each fuse line portion throughout the plane of a semiconductor substrate is also deteriorated.